From ab0db651af6f1ffa8fe96909ce16ae314d65c3fb Mon Sep 17 00:00:00 2001 From: Frans Kaashoek Date: Sun, 23 Sep 2018 08:24:42 -0400 Subject: Checkpoint port of xv6 to x86-64. Passed usertests on 2 processors a few times. The x86-64 doesn't just add two levels to page tables to support 64 bit addresses, but is a different processor. For example, calling conventions, system calls, and segmentation are different from 32-bit x86. Segmentation is basically gone, but gs/fs in combination with MSRs can be used to hold a per-core pointer. In general, x86-64 is more straightforward than 32-bit x86. The port uses code from sv6 and the xv6 "rsc-amd64" branch. A summary of the changes is as follows: - Booting: switch to grub instead of xv6's bootloader (pass -kernel to qemu), because xv6's boot loader doesn't understand 64bit ELF files. And, we don't care anymore about booting. - Makefile: use -m64 instead of -m32 flag for gcc, delete boot loader, xv6.img, bochs, and memfs. For now dont' use -O2, since usertests with -O2 is bigger than MAXFILE! - Update gdb.tmpl to be for i386 or x86-64 - Console/printf: use stdarg.h and treat 64-bit addresses different from ints (32-bit) - Update elfhdr to be 64 bit - entry.S/entryother.S: add code to switch to 64-bit mode: build a simple page table in 32-bit mode before switching to 64-bit mode, share code for entering boot processor and APs, and tweak boot gdt. The boot gdt is the gdt that the kernel proper also uses. (In 64-bit mode, the gdt/segmentation and task state mostly disappear.) - exec.c: fix passing argv (64-bit now instead of 32-bit). - initcode.c: use syscall instead of int. - kernel.ld: load kernel very high, in top terabyte. 64 bits is a lot of address space! - proc.c: initial return is through new syscall path instead of trapret. - proc.h: update struct cpu to have some scratch space since syscall saves less state than int, update struct context to reflect x86-64 calling conventions. - swtch: simplify for x86-64 calling conventions. - syscall: add fetcharg to handle x86-64 calling convetions (6 arguments are passed through registers), and fetchaddr to read a 64-bit value from user space. - sysfile: update to handle pointers from user space (e.g., sys_exec), which are 64 bits. - trap.c: no special trap vector for sys calls, because x86-64 has a different plan for system calls. - trapasm: one plan for syscalls and one plan for traps (interrupt and exceptions). On x86-64, the kernel is responsible for switching user/kernel stacks. To do, xv6 keeps some scratch space in the cpu structure, and uses MSR GS_KERN_BASE to point to the core's cpu structure (using swapgs). - types.h: add uint64, and change pde_t to uint64 - usertests: exit() when fork fails, which helped in tracking down one of the bugs in the switch from 32-bit to 64-bit - vectors: update to make them 64 bits - vm.c: use bootgdt in kernel too, program MSRs for syscalls and core-local state (for swapgs), walk 4 levels in walkpgdir, add DEVSPACETOP, use task segment to set kernel stack for interrupts (but simpler than in 32-bit mode), add an extra argument to freevm (size of user part of address space) to avoid checking all entries till KERNBASE (there are MANY TB before the top 1TB). - x86: update trapframe to have 64-bit entries, which is what the processor pushes on syscalls and traps. simplify lgdt and lidt, using struct desctr, which needs the gcc directives packed and aligned. TODO: - use int32 instead of int? - simplify curproc(). xv6 has per-cpu state again, but this time it must have it. - avoid repetition in walkpgdir - fix validateint() in usertests.c - fix bugs (e.g., observed one a case of entering kernel with invalid gs or proc --- x86.h | 108 +++++++++++++++++++++++++++++------------------------------------- 1 file changed, 48 insertions(+), 60 deletions(-) (limited to 'x86.h') diff --git a/x86.h b/x86.h index 07312a5..17bec0d 100644 --- a/x86.h +++ b/x86.h @@ -1,5 +1,7 @@ // Routines to let C code use special x86 instructions. +#ifndef __ASSEMBLER__ + static inline uchar inb(ushort port) { @@ -57,32 +59,16 @@ stosl(void *addr, int data, int cnt) "memory", "cc"); } -struct segdesc; - static inline void -lgdt(struct segdesc *p, int size) +lgdt(void *p) { - volatile ushort pd[3]; - - pd[0] = size-1; - pd[1] = (uint)p; - pd[2] = (uint)p >> 16; - - asm volatile("lgdt (%0)" : : "r" (pd)); + asm volatile("lgdt (%0)" : : "r" (p) : "memory"); } -struct gatedesc; - static inline void -lidt(struct gatedesc *p, int size) +lidt(void *p) { - volatile ushort pd[3]; - - pd[0] = size-1; - pd[1] = (uint)p; - pd[2] = (uint)p >> 16; - - asm volatile("lidt (%0)" : : "r" (pd)); + asm volatile("lidt (%0)" : : "r" (p) : "memory"); } static inline void @@ -91,11 +77,11 @@ ltr(ushort sel) asm volatile("ltr %0" : : "r" (sel)); } -static inline uint +static inline uint64 readeflags(void) { - uint eflags; - asm volatile("pushfl; popl %0" : "=r" (eflags)); + uint64 eflags; + asm volatile("pushf; pop %0" : "=r" (eflags)); return eflags; } @@ -133,51 +119,53 @@ xchg(volatile uint *addr, uint newval) static inline uint rcr2(void) { - uint val; - asm volatile("movl %%cr2,%0" : "=r" (val)); + uint64 val; + asm volatile("mov %%cr2,%0" : "=r" (val)); return val; } static inline void -lcr3(uint val) +lcr3(uint64 val) +{ + asm volatile("mov %0,%%cr3" : : "r" (val)); +} + +static inline void +writegs(uint16 v) { - asm volatile("movl %0,%%cr3" : : "r" (val)); + __asm volatile("movw %0, %%gs" : : "r" (v)); } + //PAGEBREAK: 36 // Layout of the trap frame built on the stack by the // hardware and by trapasm.S, and passed to trap(). struct trapframe { - // registers as pushed by pusha - uint edi; - uint esi; - uint ebp; - uint oesp; // useless & ignored - uint ebx; - uint edx; - uint ecx; - uint eax; - - // rest of trap frame - ushort gs; - ushort padding1; - ushort fs; - ushort padding2; - ushort es; - ushort padding3; - ushort ds; - ushort padding4; - uint trapno; - - // below here defined by x86 hardware - uint err; - uint eip; - ushort cs; - ushort padding5; - uint eflags; - - // below here only when crossing rings, such as from user to kernel - uint esp; - ushort ss; - ushort padding6; -}; + uint64 rax; + uint64 rbx; + uint64 rcx; + uint64 rdx; + uint64 rbp; + uint64 rsi; + uint64 rdi; + uint64 r8; + uint64 r9; + uint64 r10; + uint64 r11; + uint64 r12; + uint64 r13; + uint64 r14; + uint64 r15; + uint64 trapno; + uint64 err; + uint64 rip; + uint16 cs; + uint16 padding[3]; + uint64 rflags; + uint64 rsp; + uint64 ss; +}__attribute__((packed)); + +#endif + +#define TF_CS 144 // offset in trapframe for saved cs -- cgit v1.2.3