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| author | Robert Morris <rtm@csail.mit.edu> | 2019-06-05 11:42:03 -0400 |
|---|---|---|
| committer | Robert Morris <rtm@csail.mit.edu> | 2019-06-05 11:42:03 -0400 |
| commit | f1a727b971a59bab6025b4c4111342c27356ca40 (patch) | |
| tree | d22d52c613bfc003e6fb75b5d137aeff9d954201 /picirq.c | |
| parent | ec3d3a1fceee437c640f9c5c05fc517edfb1899e (diff) | |
| download | xv6-labs-2022-f1a727b971a59bab6025b4c4111342c27356ca40.tar.xz xv6-labs-2022-f1a727b971a59bab6025b4c4111342c27356ca40.zip | |
start at support for multiple CPUs
Diffstat (limited to 'picirq.c')
| -rw-r--r-- | picirq.c | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/picirq.c b/picirq.c deleted file mode 100644 index e26957f..0000000 --- a/picirq.c +++ /dev/null @@ -1,19 +0,0 @@ -#include "types.h" -#include "x86.h" -#include "traps.h" - -// I/O Addresses of the two programmable interrupt controllers -#define IO_PIC1 0x20 // Master (IRQs 0-7) -#define IO_PIC2 0xA0 // Slave (IRQs 8-15) - -// Don't use the 8259A interrupt controllers. Xv6 assumes SMP hardware. -void -picinit(void) -{ - // mask all interrupts - outb(IO_PIC1+1, 0xFF); - outb(IO_PIC2+1, 0xFF); -} - -//PAGEBREAK! -// Blank page. |